The accelerators, networking silicon and interconnect that AI training runs on.
A modern AI cluster is not a collection of chips. It is a machine in which tens of thousands of processors have to behave as one, and the constraint that decides its performance is rarely raw arithmetic. It is how fast data reaches the arithmetic, and how fast partial results move between processors.
The accelerator is the visible layer: the processor that performs the matrix multiplications underlying every neural network. Two designs compete. The general purpose parallel processor, descended from graphics hardware, runs any model and carries a mature software ecosystem that most researchers already know. The custom accelerator, designed for one operator's own workloads, trades flexibility for efficiency on the models that operator actually runs. The largest cloud providers pursue both, buying merchant silicon while designing their own.
Around the accelerator sits memory bandwidth. Model weights have to be fed to the processor continuously, and conventional memory cannot supply them fast enough, so high bandwidth memory is stacked vertically and bonded directly beside the compute die. This packaging step, not wafer fabrication, has repeatedly been the binding constraint on how many accelerators the industry can ship.
Then comes networking and interconnect, the layer that decides whether a cluster scales. Inside a server rack, processors are linked by proprietary high speed fabrics. Between racks, the traffic runs over ethernet switching silicon and optical transceivers. Retimers and active cables preserve signal integrity over distances where copper alone degrades. As clusters grow, a rising share of total system cost moves from the accelerator to everything connecting the accelerators, which is why component suppliers in this layer have grown faster than the processor market itself.
Beneath all of it sits manufacturing. Leading edge logic is fabricated by a very small number of foundries, and advanced packaging capacity is scarcer still. Processor designers compete for allocation from the same suppliers, which means capacity decisions taken years in advance constrain everyone at once.
The demand driving the entire structure is capital expenditure by cloud providers and large model developers, disclosed quarterly and revised often. That spending is a single concentrated source of demand, which is the sector's principal risk as well as its engine.
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